Staff Engineer, Analog Layout

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Design and optimize analog mixed-signal layouts such as high-speed ADCs, PLLs, bandgap voltage references, LDOs, high-speed I/O circuits, general I/Os, and ESD structures in deep sub-micron CMOS technologies using Cadence or Synopsys tools
• Collaborate closely with circuit designers and other teams to meet project specifications and timelines
• Responsible for floor planning, custom layout, and verifying compliance with design rules and schematics, including DRC, LVS, ANT, LUP, ESD, and PERC
• Maintain detailed documentation of layout methodologies, design decisions, and verification results

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering, or related fields with 3-5+ years of relevant professional experience.

• Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 2-3+ years of experience is preferred.

• Experience in analog/mixed-signal layout design for deep sub-micron CMOS circuits.

• Familiarity with advanced process technologies and FinFET is a plus.

• Proficient in block level floor planning and capable of driving the project through tape-out.Proficiency in chip level floor planning a plus.

• Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption. Layouts may include analog blocks, such as high-speed digital, high-speed ADCs, PLLs, bandgap voltage references, LDOs, I/O circuits, general I/Os, and ESD structures.

• Understanding techniques to manage IR drop, RC delay, electro-migration, self-heating, and crosstalk

• Experience with full chip layout and verification

• Proficiency with CAD tools such as Cadence "Virtuoso," Mentor Graphics "Calibre," or Synopsys "Custom Compiler."

• Strong proficiency in interpreting DRC, ERC, LVS, LUP, and PERC reports

• Ability to work independently with strong analytical skills, creative thinking, and self-motivation

• Ability to work across teams

• Strong communication skills

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.