Principal Physical Design Engineer
 Microsoft | |
 United States, North Carolina, Raleigh | |
 Oct 03, 2025 | |
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OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft's Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Physical Design Engineer with CPU Core expertise to join the team. #SCHIE #CSME #Siliconjobs #CCDO
ResponsibilitiesResponsible for Core CPU partition (L1-L2) or similar ownership with PPAS (Power, Performance, Area & Schedule) target accomplishments.Responsible for RTL to GDS implementation in Physical Design domain.Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.Lead & influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA). Drive end-to-end execution from synthesis through place-and-route for Core CPU, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. Develop and implement robust clock distribution strategies that meet design specifications. Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes. Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.Demonstrate technical expertise across various domains of Physical Design & Timing Signoff.Clear communications on project status & planning.Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion. | |