Principal Physical Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

As a Principal Physical Design Engineer specializing in chip-level Place and Route (PNR), you will play a pivotal role in defining Marvell's physical design process and flow, ensuring successful delivery of high-performance designs in advanced technology nodes. Leveraging your expertise, you'll directly influence the quality of Marvell's next-generation products, guiding backend implementation from concept to tapeout and providing technical leadership on challenging SoC projects.

• Hands-On Chip-Level Physical Design:

• Lead chip-level PNR activities, from floor planning and power grid design to clock tree synthesis, routing, and timing closure.
• Perform detailed timing, power and signal integrity signoff, including IR drop and crosstalk analysis, ensuring designs meet stringent performance and reliability targets.
• Manage physical verification tasks (DRC, LVS, antenna) to meet process and quality standards required for advanced semiconductor nodes.

• Leadership and Collaboration:

• Act as a technical leader, guiding a team of physical design engineers on project-level backend implementation, and coordinate with frontend, integration, and verification teams.
• Develop and refine physical design methodologies and flows, collaborating cross-functionally to optimize design efficiency and alignment with project goals.
• Mentor and develop junior engineers, fostering an environment that encourages innovation and excellence.

• Process and Tool Optimization:
• Use scripting skills to streamline and automate workflows (Makefile, Tcl, Perl), enhancing design efficiency across projects.
• Maintain a deep understanding of physical design tools, including Cadence Innovus, Synopsys IC Compiler, and Fusion Compiler, ensuring best practices in tool use and integration.

At Marvell, you'll have the opportunity to work on industry-leading designs, pushing the boundaries of what's possible in the semiconductor field. This Principal Physical Design Engineer role offers an impactful platform to shape Marvell's next generation of products and lead a team committed to excellence and innovation.

What We're Looking For

• Education & Experience:
• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
• 10+ years of hands-on experience in physical design and verification, with proven success in chip-level PNR and tape-outs of complex SoC designs.

• Technical Expertise:
• Demonstrated ability to lead chip-level backend implementation and deliver on schedule.
• Familiar with hierarchical design strategies and deep sub-micron technology (e.g., N7/N5), with knowledge of current design technologies used in major foundries.
• Extensive experience with timing analysis (Tempus, PrimeTime) and EM/IR-Drop/crosstalk analysis tools (Voltus, Celtic, PTSI, AstroRail).
• Skilled in physical verification tools and logic equivalence tools (LEC, Formality, Calibre) and extraction tools (QRC, StarRC).

• Programming & Automation Skills:
• Advanced scripting abilities, especially in Makefile, Tcl, and Perl, with a focus on improving backend process efficiency.

• Key Attributes:
• Detail-oriented, self-motivated, and an effective communicator, with a collaborative team-oriented approach.
• Planning, and resourcing physical design work, cross functional collaboration.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.