Staff Graphics IP Design Verification Engineer (UVM/System Verilog)

THE ROLE:

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processorarchitecture,digitaldesign. You are a team player who has excellent communication skills and experience collaborating with other engineerslocatedindifferent sites/timezones.You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Power Performance validation for AI systems, primarily windows.

• Power Performance ValidationtestPlan creation,executionand automation

• Power and performance automationfor various Windows AI workloads at test app level, Real app level and for microkernels and benchmarks.

• Collaborate closely withfirmware,IPand SOCteamstovalidateNPU IPat IP level and system level forpower and performance functionality acrosspresiliconandpostsiliconenvironments

• Will berequiredto do FW prototyping, making changes in FW,compile,testand debugfor Power/perf prototyping.

• Power kernel development and debug for AI accelerator/ NPU/GPU

• AI applications development and debug, primarily on windows.

• Debugging windows systemusing debug tools (wndbg), and traces for performance debugs will befrequentlyused.

• Use of AI tools actively for high efficiency

• Goodunderstanding of power and performance concepts at system level including CPU, NPU, GPU, memory.

• Power performance debug and tuning experiencefor various workloads,understandworkload sensitivities,and tune for most efficientperformance.

• Analyze issues spanningRTL, firmware, and software layers, drivingrootcauseanalysis and workingcrossfunctionallyto resolution.

• Contribute to the definition offirmware requirements and validation strategiesto ensure robust coverage ofrealworlduse cases.

PREFERRED EXPERIENCE:

• Good understanding of SOC architecture, Firmware,OSand Applicationcomprisingthewhole system.

• Experience working with orvalidatinglowlevelfirmware(e.g.,Power management FW,FreeRTOS, Zephyr,Microcontroller FW).

• Strong understanding ofhardware/firmware interfaces, including registers, interrupts,memorymappedI/O, and sequencing.

• Ability to read, debug, and reasonaboutC/C++ firmware codein the context of hardware validation.

• Experience collaborating with firmware or embedded software engineers to debug complexsystemlevelissues.

• Strong background in theC,C++ language,and Python,

• Handsonexperience with graphics, SoC, orIPlevelfirmware used forbringup, configuration, or power/clock management.

• Familiarity withpostsiliconvalidation,firmwareassisteddebug, orlabbasedbringupactivities.

• Experiencevalidatingsystems where firmware plays a critical role in feature enablement and performance tuning.

• Exposure to leadership or mentorship is an asset

• Prior exposure toNPU / Windows based systems with exposure to CPU, GPU, NPU power, performance

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.